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Freescale Semiconductor Advance Information
Document Number: MC33879 Rev 6.0, 6/2007
Configurable Octal Serial Switch with Open Load Detect Current Disable
The 33879 device is an 8-output hardware-configurable, high-side / low-side switch with 16-bit serial input control. Two of the outputs may be controlled directly via microprocessor for PWM applications. The 33879 incorporates SMARTMOS technology, with CMOS logic, bipolar/MOS analog circuitry, and DMOS power MOSFETs. The 33879 controls various inductive, incandescent, or LED loads by directly interfacing with a microcontroller. The circuit's innovative monitoring and protection features include very low standby currents, cascade fault reporting, internal + 45 V clamp voltage for low-side configuration, - 20 V high-side configuration, output-specific diagnostics, and independent overtemperature protection. Features * Designed to Operate 5.5 V < VPWR < 26.5 V * 16-Bit SPI for Control and Fault Reporting, 3.3 V / 5.0 V Compatible * Outputs Are Current Limited (0.6 A to 1.2 A) to Drive Incandescent Lamps * Output Voltage Clamp, + 45 V (Low Side) and - 20 V (High Side) During Inductive Switching * On/Off Control of Open Load Detect Current (LED Application) * Internal Reverse Battery Protection on VPWR * Loss of Ground or Supply Will Not Energize Loads or Damage IC * Maximum 5.0 A IPWR Standby Current at 13 V VPWR * RDS(ON) of 0.75 at 25C Typical * Short Circuit Detect and Current Limit with Automatic Retry * Independent Overtemperature Protection * Pb-Free Packaging Designated by Suffix Code EK
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+5.0 V VPWR
33879 33879A
HIGH SIDE/ LOW SIDE SWITCH
DWB SUFFIX EXPOSED PAD EK SUFFIX (PB-FREE) 98ARL10543D 32-PIN SOICW
ORDERING INFORMATION
Device MC33879EK/R2 MCZ33879EK/R2 MCZ33879AEK/R2 -40C to 125C 32 SOICW-EP Temperature Range (TA) Package
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VDD VPWR EN DI SCLK CS DO IN5 IN6 D1 D2 D3 D4 S1 S2 S3 S4
VBAT
MCU
A0 MOSI SCLK CS MISO PWM1 PWM2
High-Side Drive
M D5 D6 D7 D8 S5 S6 S7 S8
H-Bridge Configuration VBAT VBAT
Low-Side Drive
GND
Figure 1. 33879 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations (Optional Table)
Freescale Part No. 33879 33879A VPWR Supply Voltage -16 to 40V -16 to 45V Reference Location 6, 7, 13
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INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
__ CS SCLK DI DO
~50 A Internal Bias Power Supply Charge Pump Overvoltage Shutdown/POR Sleep State
VPWR
GND
OV, POR, SLEEP Typical of all 8 output drivers TLIM SPI Bit 0 ~50 A Enable SPI Bit 4 Gate Drive Control
Current Limit + -
EN
~110 k
SPI and Interface Logic
IN5
Open Load Detect Current ~80 A
D1 D2 D3 D4 D7 D8 S1 S2 S3 S4 S7 S8
Drain Outputs
IN6
~50 A
IN5
+ -
+
-
Open/Short Comparator
~4.0 V Open/Short Threshold
Source Outputs
TLIM Gate Drive Control
Current Limit + -
EP
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Exposed Pad
Open Load Detect Current ~80 A
D5 D6
Drain Outputs
S5 S6
+
+ -
Source Outputs
-
Open/Short Comparator
~4.0 V Open/Short Threshold
Figure 2. 33879 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
GND VDD S8 NC D8 S2 D2 NC NC S1 D1 D6 S6 IN6 EN SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
GND
25 24 23 22 21 20 19 18 17
DO VPWR NC S7 D7 S4 D4 NC NC S3 D3 D5 S5 IN5
CS
DI
Figure 3. 33879 Pin Connections Table 2. 33879 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Pin Number 1 2 Pin Name GND VDD S8 NC D8 S2 D2 S1 D1 D6 S6 IN6 EN SCLK DI CS IN5 S5 D5 D3 Pin Function Ground Input Formal Name Ground Logic Supply Voltage Source Output 8 Not Connected Drain Output 8 Source Output 2 Drain Output 2 Source Output 1 Drain Output 1 Drain Output 6 Source Output 6 Command Input 6 Enable Input SPI Clock Serial Data Input SPI Chip Select Command Input 5 Source Output 5 Drain Output 5 Drain Output 3 Digital ground. Logic supply for SPI interface. With VDD low the device will be in Sleep mode. Output 8 MOSFET source pin. No internal connection to this pin. Output 8 MOSFET drain pin. Output 2 MOSFET source pin. Output 2 MOSFET drain pin. Output 1 MOSFET source pin. Output 1 MOSFET drain pin. Output 6 MOSFET drain pin. Output 6 MOSFET source pin. PWM direct control input pin for output 6. IN6 is "OR" with SPI bit. IC Enable. Active high. With EN low, the device is in Sleep mode. SPI control clock input pin. SPI control data input pin from MCU to the 33879. Logic [1] activates output. SPI control chip select input pin from MCU to the 33879. Logic [0] allows data to be transferred in. PWM direct control input pin for output 5. IN5 is "OR" with SPI bit. Output 5 MOSFET source pin. Output 5 MOSFET drain pin. Output 3 MOSFET drain pin. Definition
3 4, 8, 9, 24, 25, 30 5 6 www..com 7 10 11 12 13 14 15 16 17 18 19 20 21 22
Output No Connection Output Output Output Output Output Output Output Input Input Clock Input Input Input Output Output Output
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PIN CONNECTIONS
Table 2. 33879 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Pin Number 23 26 27 28 29 31 Pin Name S3 D4 S4 D7 S7 VPWR DO EP Pin Function Output Output Output Output Output Input Formal Name Source Output 3 Drain Output 4 Source Output 4 Drain Output 7 Source Output 7 Battery Input Output 3 MOSFET source pin. Output 4 MOSFET drain pin. Output 4 MOSFET source pin. Output 7 MOSFET drain pin. Output 7 MOSFET source pin. Power supply pin to the 33879. VPWR has internal reverse battery protection. SPI control data output pin from the 33879 to the MCU. DO = 0 no fault, DO = 1 specific output has fault. Device will perform as specified with the Exposed Pad un-terminated (floating) however, it is recommended that the Exposed Pad be terminated to pin 1 (GND) and system ground. Definition
32 33
Output Ground
Serial Data Output Exposed Pad
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. 33879 Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS VDD Supply Voltage (1)
CS, DI, DO, SCLK, IN5, IN6, and EN (1)
Symbol
Value
Unit
VDD - VPWR 33879 33879A
- 0.3 to 7.0 - 0.3 to 7.0
VDC VDC VDC
VPWR Supply Voltage
(1)
-16 to 40 -16 to 45 ECLAMP VESD1 VESD2 VESD1 VESD2 50 mJ V
Output Clamp Energy (2) ESD Voltage
(3)
Human Body Model Machine Model Human Body Model Machine Model THERMAL RATINGS Operating Temperature Ambient Junction Case Storage Temperature Power Dissipation
(4)
33879 33879 33879A 33879A
450 100 2000 200
C
TA TJ TC TSTG PD RJA RJC TPPRT - 40 to 125 - 40 to 150 - 40 to 125 - 55 to 150 1.7 71 1.2 Note 6 C
C
W
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Junction to Ambient Between the Die and the Exposed Die Pad Peak Package Reflow Temperature During Reflow (5), (6)
C/W
Notes 1. Exceeding these limits may cause malfunction or permanent damage to the device. 2. Maximum output clamp energy capability at 150C junction temperature using single non-repetitive pulse method with I = 350 mA. 3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 4. 5. 6. Maximum power dissipation at TA = 25C with no heatsink used. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics Characteristics noted under conditions 3.1 V VDD 5.5 V, 5.5 V VPWR 18 V, - 40C TC 125C unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.
Characteristic POWER INPUT Supply Voltage Range Fully Operational 33879 33879A Supply Current Sleep State Supply Current VDD or EN 0.8 V, VPWR = 13 V Sleep State Supply Current EN 0.8 V, VDD = 5.5 V VPWR Overvoltage Shutdown Threshold Voltage 33879 33879A VPWR Overvoltage Shutdown Hysteresis Voltage VPWR Undervoltage Shutdown Threshold Voltage VPWR Undervoltage Shutdown Hysteresis Voltage Logic Supply Voltage Logic Supply Current Logic Supply Sleep State Threshold Voltage VPWR(OV-HYS) VPWR(UV) VPWR(UV-HYS) VDD IDD VDD(SS) VPWR(OV) 27 28 0.2 3.0 300 3.1 250 0.8 28.5 30 1.5 4.0 500 - 400 2.5 32 33 2.5 5.0 700 5.5 700 3.0 V V mV V A V IVDD (SS) - 2.0 5.0 V IPWR (ON) IPWR (SS) - 2.0 5.0 A VPWR (FO) 5.5 5.5 - - - 14 26.5 27.5 24 mA A V Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.1 V VDD 5.5 V, 5.5 V VPWR 18 V, - 40C TC 125C unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.
Characteristic POWER OUTPUT Drain-to-Source ON Resistance (IOUT = 0.350 A, VPWR = 13 V) TJ = 125C TJ = 25C TJ = -40C Output Self Limiting Current High-Side and Low-Side Configurations Output Fault Detection Voltage Threshold (7) Outputs Programmed OFF Output Fault Detection Current @ Threshold, High-Side Configuration Outputs Programmed OFF Output Fault Detection Current @ Threshold, Low-Side Configuration Outputs Programmed OFF Output OFF Open Load Detection Current, High-Side Configuration VDRAIN = 16 V, VSOURCE = 0 V, Outputs Programmed OFF, VPWR=16V Output OFF Open Load Detection Current, Low-Side Configuration VDRAIN = 16 V, VSOURCE = 0 V, Outputs Programmed OFF, VPWR=16V Output Clamp Voltage Low-Side Drive ID = 10 mA Output Clamp Voltage High-Side Drive IS = -10 mA Output Leakage Current High-Side and Low-Side Configurations www..com VDD = 0 V, VDRAIN = 16 V, VSOURCE = 0 V Output Leakage Current Low-Side Configuration VDD = 5.0 V, VDRAIN = 16 V, VSOURCE = 0 V, Open Load Detection Current Disabled Output Leakage Current High-Side Configuration VDD = 5.0 V, VDRAIN = 16 V, VSOURCE = 0 V, Open Load Detection Current Disabled Overtemperature Shutdown (8) Overtemperature Shutdown Hysteresis (8) TLIM TLIM (HYS) IOUT (LKG) - 155 5.0 - - 10 20 185 15 IOUT (LKG) - IOUT (LKG) - - 5.0 A - 5.0 A VOC (HSD) -15 - 20 - 25 A VOC (LSD) 40 45 55 V IOCO 40 75 135 IOCO 65 100 160 A IOUT(FLT-TH) 20 30 60 A IOUT(FLT-TH) 35 55 90 A IOUT (LIM) VOUT(FLT-TH) 2.5 4.0 4.5 A RDS (ON) - - - 0.6 - 0.75 - - 1.4 - - 1.2 A V Symbol Min Typ Max Unit
V
C C
Notes 7. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts. 8. This parameter is guaranteed by design; however, it is not production tested.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.1 V VDD 5.5 V, 5.5 V VPWR 18 V, - 40C TC 125C unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.
Characteristic DIGITAL INTERFACE Input Logic High-Voltage Thresholds (9) Input Logic Low-Voltage Thresholds (9) IN5, IN6, EN Input Logic Current IN5, IN6, EN = 0 V IN5, IN6 Pulldown Current 0.8 V to 5.0 V EN Pulldown Current EN = 5.0 V SCLK, DI Input, Tri-State DO Output 0 V to 5.0 V CS Input Current CS = VDD CS Pullup Current CS = 0 V CS Leakage Current to VDD CS = 5.0 V, VDD = 0 V DO High-State Output Voltage IDO-HIGH = -1.6 mA DO Low-State Output Voltage IDO-LOW = 1.6 mA Input Capacitance on SCLK, DI, Tri-State DO, IN5, IN6, EN (10) www..com CIN VDOLOW - - - - 0.4 20 pF VDOHIGH VDD - 0.4 - VDD V ICS(LKG) - - 10 V ICS -30 - -100 A I SCK, I DI, I TRIDO
Symbol
Min
Typ
Max
Unit
VIH VIL I IN5, I IN6, I EN
0.7 VDD GND - 0.3
- -
VDD + 0.3 0.2 VDD
V V A
-10 I IN5, I IN6, 30 I EN 20
-
10 A
45
100 A
45
100 A
-10
-
10 A
ICS -10 - 10
A
Notes 9. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN. 10. This parameter is guaranteed by design; however, it is not production tested.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V VDD 5.5 V, 5.5 V VPWR 18 V, - 40C TC 125C unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.
Characteristic POWER OUTPUT TIMING Output Slew Rate Low-Side Configuration (11) RLOAD = 620 , CL = 200 pF Output Slew Rate Low-Side Configuration (11) RLOAD = 620 , CL = 200 pF Output Rise Time High-Side Configuration (11) RLOAD = 620 , CL = 200 pF Output Fall Time High-Side Configuration (11) RLOAD = 620 , CL = 200 pF Output Turn ON Delay Time, High-Side and Low-Side Configuration (12) Output Turn OFF Delay Time, High-Side and Low-Side Configuration (12) Output Fault Delay Time (13) Power-ON Reset Delay Delay Time Required from Rising Edge of EN and VDD to SPI Active Low-State Duration on VDD or EN for Reset VDD or EN 0.2 V t RESET 100 - - Symbol Min Typ Max Unit
t SR(RISE)
0.1 0.5 1.0
V/s
t SR(FALL)
0.1 0.5 1.0
V/s
t SR(RISE)
0.1 0.3 1.0
V/s
t SR(FALL)
0.1 0.3 1.0
V/s
t DLY(ON)
1.0 15 50
s s 1.0 30 - 100 300 s s 100 - - s
t DLY(OFF) t FAULT
tPOR 100
Notes 11. Output slew rate respectively measured across a 620 resistive load at 10 to 90 percent and 90 to 10 percent voltage points. CL www..com is connected from Drain or Source output to Ground. capacitor 12. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to the beginning of the 10 and 90 percent transition points. 13. Duration of fault before fault bit is set. Duration between access times must be greater than 300 s to read faults.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 3.1 V VDD 5.5 V, 5.5 V VPWR 18 V, - 40C TC 125C unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.
Characteristic DIGITAL INTERFACE TIMING
(14)
Symbol
Min
Typ
Max
Unit
Recommended Frequency of SPI Operation (14) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) DI to Falling Edge of SCLK (Required Setup Time) Falling Edge of SCLK to DI (Required Hold Time) DI, CS, SCLK Signal Rise Time (15) DI, CS, SCLK Signal Fall Time (15) Time from Falling Edge of CS to DO Low Impedance (16) Time from Rising Edge of CS to DO High Impedance (17) Time from Rising Edge of SCLK to DO Data Valid (18) Notes 14. 15. 16. 17. 18.
f SPI t LEAD t LAG t DI (SU) t DI (HOLD) t R (DI) t F (DI) t DO (EN) t DO (DIS) t VALID
- 100 50 16 20 - - - - -
4.0 - - - - 5.0 5.0 - - 25
- - - - - - - 55 55 55
MHz ns ns ns ns ns ns ns ns ns
This parameter is guaranteed by design. Production test equipment uses 4.16 MHz, 5.5 V/3.1 V SPI interface. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at DO pin. Time required for output status data to be terminated at DO pin. Time required to obtain valid data out from DO following the rise of SCLK.
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
CS
0.2 VDD
tLEAD
tLAG
SCLK
0.7 VDD 0.2 VDD
tDI(SU) tDI(HOLD)
DI
0.7 VDD 0.2 VDD
MSB in
tDO(EN)
tVALID
tDO(DIS)
DO
0.7 VDD 0.2 VDD
MSB out Figure 4. SPI Timing Diagram
LSB out
VDD = 5.0 V
SCLK
tR(DI) 0.7 VDD
< 50 ns 50%
tF(DI
< 50 ns 3.3/5.0 V 0.2 VDD 0V VOH VOL
SCLK
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DO CL = 200 pF 0.7 VDD DO (Low-to-High) DO (High-to-Low) 0.7 VDD 0.2 0.2 VDD tR(DO tVALID
VOH VOL
NOTE: CL represents the total capacitance of the test www..com fixture and probe.
Figure 5. Valid Data Delay Time and Valid Time Test Circuit
tF(CS) < 50 ns CS 0.2 VDD DO (Tri-State to Low) 90% 10% tDO(EN) 90% tR(CS) < 50 ns
Figure 6. Valid Data Delay Time and Valid Time Waveforms
3.3/5.0 V 0.7 VDD 0V tDO(DIS) VTri-State
10% tDO(EN) 90% DO (Tri-State to High) 10% tDO(DIS)
VOL VOH
VTri-State
Figure 7. Enable and Disable Time Waveforms
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ELECTRICAL CHARACTERISTICS TYPICAL ELECTRICAL CHARACTERISTICS
TYPICAL ELECTRICAL CHARACTERISTICS
20 IPWR Current into VPWR Pin (mA) IPWR Current into VPWR Pin (A)
VPWR @ 18 V
7
VPWR @ 13 V
19 18 17 16 15 14 -40 -25 0 25 50 75 100 125
33879A 33879
6 5 4 3 2 1 -40 -25 0 25 50 75 100 125
TA, Ambient Temperature (C) Figure 8. IPWR vs. Temperature
TA, Ambient Temperature (C) Figure 9. Sleep State IPWR vs. Temperature
140 IPWR Current into VPWR Pin (A)
TA = 25C
1.4 1.2 1.0
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VPWR @ 13 V High Side Drive
120 RDS(ON) () 100 80 60 40 20 0 5 10 15 VPWR
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0.8 0.6 0.4
20
25
-40 -25
0 25 50 75 100 TA, Ambient Temperature (C)
125
Figure 10. Sleep State IPWR vs. VPWR www..com
Figure 11. RDS(ON) vs. Temperature at 350 mA
1.4 1.2 1.0 RDS(ON) () 0.8 0.6 0.4 0.2 0
TA = 25C High Side Drive
5
10
15
20
25
VPWR (V) Figure 12. RDS(ON) vs. VPWR at 350 mA
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ELECTRICAL CHARACTERISTICS TYPICAL ELECTRICAL CHARACTERISTICS
VOUT(flt-th), Open Load Threshold (V)
140
VPWR @ 13 V
5.5 5.0 4.5 4.0 3.5 3.0 2.5
IOCO, Open Load (A)
120 100 80 60
High Side
VPWR @ 13 V High Side and Low Side
40 20 -40 -25 0 25 50 75
Low Side
100
125
-40 -25
0
25
50
75
100
125
TA, Ambient Temperature (C) Figure 13. Open Load Detection Current at Threshold
TA, Ambient Temperature (C) Figure 14. Open Load Detection Threshold vs. Temperature
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION CS PIN
The system MCU selects the 33879 with which to communicate through the use of the chip select CS pin. Logic low on CS enables the data output (DO) driver and allows data to be transferred from the MCU to the 33879 and vice versa. Data clocked into the 33879 is acted upon on the rising edge of CS. To avoid any spurious data, it is essential the high-to-low transition of the CS signal occur only when SPI clock (SCLK) is in a logic low state. Load Detection Current disabled will report logic [0] in the off state. The first eight positive transitions of SCLK will report logic [0] followed by the status of the eight output drivers. The DI / DO shifting of data follows a first-in, first-out protocol with both input and output words transferring the most significant bit (MSB) first.
EN PIN
The EN pin on the 33879 enables the device. With the EN pin high, output drivers may be activated and open / short fault detection performed and reported. With the EN pin low, all outputs become inactive, Open Load Detection Current is disabled, and the device enters Sleep mode. The 33879 will perform Power-ON Reset on rising edge of the enable signal.
SCLK PIN
The SCLK pin clocks the internal shift registers of the 33879. The serial data input (DI) pin is latched into the input shift register on the falling edge of the SCLK. The serial data output (DO) pin shifts data out of the shift register on the rising edge of the SCLK signal. False clocking of the shift register must be avoided to ensure validity of data. It is essential that the SCLK pin be in a logic low state when the CS pin makes any transition. For this reason, it is recommended the SCLK pin is commanded to a logic low state when the device is not accessed (CS in logic high state). With CS in a logic high state, signals present on SCLK and DI are ignored and the DO output is tri-state.
IN5 AND IN6 PINS
The IN5 and IN6 command inputs allow outputs five and six to be used in PWM applications. The IN5 and IN6 pins are OR-ed with the Serial Peripheral Interface (SPI) command input bits. For SPI control of outputs five and six, the IN5 and IN6 pins should be grounded or held low by the microprocessor. When using IN5 or IN6 to PWM the output, the control SPI bit must be logic [0]. Maximum PWM frequency for each output is 2.0 kHz.
DI PIN
The DI pin is used for serial instruction data input. DI information is latched into the input register on the falling edge of SCLK. A logic high state present on DI will program a specific output on. The specific output will turn on with the rising edge of the CS signal. Conversely, a logic low state www..com present on the DI pin will program the output off. The specific output will turn off with the rising edge of the CS signal. To program the eight outputs and Open Load Detection Current on or off, send the DI data beginning with the Open Load Detection Current bits, followed by output eight, output seven, and so on to output one. For each falling edge of the SCLK while CS is logic low, a data bit instruction (on or off) is loaded into the shift register per the data bit DI state. Sixteen bits of entered information is required to fill the input shift register.
VDD PIN
The VDD input pin is used to determine logic levels on the microprocessor interface (SPI) pins. Current from VDD is used to drive DO output and the pullup current for CS. VDD must be applied for normal mode operation. The 33879 device will perform Power-ON Reset with the application of VDD.
VPWR PIN
The VPWR pin is battery input and Power-ON Reset to the 33879 IC. The VPWR pin has internal reverse battery protection. All internal logic current is provided from the VPWR pin. The 33879 will perform Power-ON Reset with the application of VPWR.
D1- D8 PINS
The D1 to D8 pins are the open-drain outputs of the 33879. For high-side drive configurations, the drain pins are connected to battery supply. In low-side drive configurations, the drain pins are connected to the low side of the load. All outputs may be configured individually as desired. When configured as low-side drive, the 33879 limits the positive inductive transient to 45 V.
DO PIN
The DO pin is the output from the shift register. The DO pin remains tri-state until the CS pin is in a logic low state. All faults on the 33879 device are reported as logic [1] through the DO data pin. Regardless of the configuration of the driver, open loads and shorted loads are reported as logic [1]. Conversely, normal operating outputs with non-faulted loads are reported as logic [0]. Outputs programmed with Open
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FUNCTIONAL DESCRIPTION MCU INTERFACE DESCRIPTION
S1- S8 PINS
The S1 to S8 pins are the source outputs of the 33879. For high-side drive configurations, the source pins are connected directly to the load. In low-side drive configurations, the source is connected to ground. All outputs may be configured individually as desired. When high-side drive is used, the 33879 will limit the negative inductive transient to negative 20 V.
EXPOSED PAD PIN
Device will perform as specified with the Exposed Pad unterminated (floating) however, it is recommended that the Exposed Pad be terminated to pin 1 (GND) and system ground.
MCU INTERFACE DESCRIPTION INTRODUCTION
The 33879 is an 8-output hardware-configurable power switch with 16-bit serial control. A simplified internal block diagram of the 33879 is shown in Figure 2 on page 3. The 33879 device uses high-efficiency up-drain power DMOS output transistors exhibiting low drain-to-source ON resistance (RDS(ON) = 0.75 at 25C typical) and dense CMOS control logic. All outputs have independent voltage clamps to provide fast inductive turn-off and transient protection. In operation, the 33879 functions as an 8-output serial switch serving as a MCU bus expander and buffer with fault management and fault reporting features. In doing so, the device directly relieves the MCU of the fault management functions. This device directly interfaces to an MCU using a SPI for control and diagnostic readout. Figure 15 illustrates the basic SPI configuration between an MCU and one 33879.
MC68HCxx Microcontroller
All inputs are compatible with 5.0 V and 3.3 V CMOS logic levels and incorporate positive logic. When a SPI bit is programmed to a logic [0], the corresponding output will be OFF. Conversely, when a SPI bit is programmed to logic [1] the output being controlled will be ON. Diagnostics are treated in a similar manner. Outputs with a fault will feed back (via DO) a logic [1] to the microcontroller, while normal operating outputs will provide a logic [0]. Figure 16 illustrates the daisy chain configuration using the 33879. Data from the MCU is clocked daisy chain through each device while the CS bit is commanded low by the MCU. During each clock cycle, output status from the daisy chain is transferred to the MCU via the Master In Slave Out (MISO) line. On rising edge of CS, command data stored in the input register is then transferred to the output driver.
SCLK Parallel Port
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33879 CS MC68HCxx MISO Microcontroller DO with SPI Interface
33879 CS SCLK DI
33879 CS DO SCLK DI
DI
DO
MOSI
DI Shift Register
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Shift Register MISO
16 Bits
8 Outputs MOSI
8 Outputs
8 Outputs
DO
16 Bits
SCLK Receive Buffer Parallel Ports CS To Logic
Figure 16. 33879 SPI System Daisy Chain Multiple 33879 devices can be controlled in a parallel input fashion using the SPI. Figure 17 illustrates the control of 24 loads using three dedicated parallel MCU ports for chip select.
Figure 15. SPI Interface with Microcontroller
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION SPI DEFINITION
33879 MOSI SCLK MISO MC68HCxx Microcontroller with SPI Interface DI SCLK DO CS 33879 DI SCLK DO CS 33879 A Parallel Ports B C DI SCLK DO CS 8 Outputs 8 Outputs 8 Outputs
Figure 17. Parallel Input SPI Control
SPI DEFINITION
On each SPI communication, a 16-bit command word is sent to the 33879 and a 16-bit status word is received from the 33879. The MSB is sent and received first. As Table 6 shows, the Command Register defines the position and operation the 33879 will perform on rising edge of CS. The Fault Register, shown in Table 7, defines the previous state status of the output driver. Table 8 identifies the type of fault and the method by which the fault is communicated to the microprocessor.
Table 6. Command Register Definition
MSB Bit 15 Bit 14 Bit 13
ON / OFF Open Load Detect 6
LSB Bit 12
ON / OFF Open Load Detect 5
Bit 11
ON / OFF Open Load Detect 4
Bit 10
ON / OFF Open Load Detect 3
Bit 9
ON / OFF Open Load Detect 2
Bit 8
ON / OFF Open Load Detect 1
Bit 7
ON / OFF OUT 8
Bit 6
ON / OFF OUT 7
Bit 5
ON / OFF OUT 6
Bit 4
ON / OFF OUT 5
Bit 3
ON / OFF OUT 4
Bit 2
ON / OFF OUT 3
Bit 1
ON / OFF OUT 2
Bit 0
ON / OFF OUT 1
ON / ON / OFF OFF Open Open Load Load Detect Detect 8 7 www..com
0 = Bits 0 to 7, Output commanded OFF. 0 = Bits 8 to 15, Open Load Detection Current OFF.
1 = Bits 0 to 7, Output commanded ON. 1 = Bits 8 to 15 Open Load Detection Current ON.
Table 7. Fault Register Definition
MSB Bit 15
0
LSB Bit 14
0
Bit 13
0
Bit 12
0
Bit 11
0
Bit 10
0
Bit 9
0
Bit 8
0
Bit 7
OUT 8 Status
Bit 6
OUT 7 Status
Bit 5
OUT 6 Status
Bit 4
OUT 5 Status
Bit 3
OUT 4 Status
Bit 2
OUT 3 Status
Bit 1
OUT 2 Status
Bit 0
OUT 1 Status
0 = Bits 0 to 7, No Fault at Output. 1 = Bits 0 to 7, Output Short-to-Battery, Short-to-GND, Open Load, or TLIM.
Bits 8 to 15 will always return "0".
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FUNCTIONAL DESCRIPTION SPI DEFINITION
Table 8. Fault Operation Serial Output (DO) Pin Reports
Overtemperature Overcurrent Output ON Open Load Fault Output OFF Open Load Fault Fault reported by serial output (DO) pin. DO pin reports short to battery/supply or overcurrent condition. Not reported. DO pin reports output OFF open load condition only with Open Load Detection Current enabled. DO pin will report "0" for Output OFF Open Load Fault with Open Load Detection Current disabled.
Device Shutdowns
Overvoltage Total device shutdown at VPWR = VPWR(OV) V. Resumes normal operation with proper voltage. All outputs assuming the previous state upon recovery from overvoltage. Overtemperature Only the output experiencing an overtemperature shuts down. Output assumes previous state upon recovery from overtemperature.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION DEVICE OPERATION
DEVICE OPERATION POWER SUPPLY
The 33879 device has been designed with ultra-low Sleep mode currents. The device may enter Sleep mode via the EN pin or the VDD pin. In the Sleep mode (EN or VDD 0.8 V), the current consumed by the VPWR pin is less than 5.0 A. Placing the 33879 in Sleep mode resets the internal registers to the Power-ON Reset state. The reset state is defined as all outputs off and Open Load Detection Current disabled. To place the 33879 in the Sleep mode, either command all outputs off and apply logic low to the EN input pin or remove power from the VDD supply pin. Prior to removing VDD from the device, it is recommended that all control inputs from the MCU be low.
SPI INTEGRITY CHECK
Checking the integrity of the SPI communication with the initial power-up of the VDD and EN pins is recommended. After initial system start-up or reset, the MCU will write one 32-bit pattern to the 33879. The first 16 bits read by the MCU will be 8 logic [0]s followed by the fault status of the outputs. The second 16 bits will be the same bit pattern sent by the MCU. By the MCU receiving the same bit pattern it sent, bus integrity is confirmed. Please note the second 16-bit pattern the MCU sends to the device is the command word and will be transferred to the outputs with rising edge of CS. Important A SCLK pulse count strategy has been implemented to ensure integrity of SPI communications. SPI messages consisting of 16 SCLK pulses and multiples of 8 clock pulses thereafter will be acknowledged. SPI messages consisting of other than 16 + multiples of 8 SCLK pulses will be ignored by the device.
PARALLELING OF OUTPUTS
Using MOSFETs as an output switch conveniently allows the paralleling of outputs for increased current capability. RDS(ON) of MOSFETs have an inherent positive temperature coefficient that provides balanced current sharing between outputs without destructive operation. This mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. Performance of parallel operation results in a corresponding decrease in RDS(ON) while the output OFF Open Load Detection Currents and the output current limits increase correspondingly. Paralleling outputs from two or more different IC devices is possible but not recommended.
OVERTEMPERATURE FAULT
Overtemperature detection and shutdown circuits are specifically incorporated for each individual output. The shutdown following an overtemperature condition is independent of the system clock or any other logic signal. Each independent output shuts down at 155C to 185C. When an output shuts down owing to an overtemperature fault, no other outputs are affected. The MCU recognizes the fault by a one in the fault status register. After the 33879 device has cooled below the switch point temperature and 15C hysteresis, the output will activate unless told otherwise by the MCU via SPI to shut down.
FAULT LOGIC OPERATION
Fault logic of the 33879 device has been greatly simplified over other devices using SPI communications. As command word one is being written into the shift register, a fault status word is being simultaneously written out and received by the www..com MCU. Regardless of the configuration, with no outputs faulted and Open Load Detection Current enabled, all status bits being received by the MCU will be zero. When outputs are faulted (off state open circuit or on state short circuit / overtemperature), the status bits being received by the MCU will be one. The distinction between open circuit fault and short / overtemperature is completed via the command word. For example, when a zero command bit is sent and a one fault is received in the following word, the fault is open / shortto-battery for high-side drive or open / short-to-ground for lowside drive. In the same manner, when a one command bit is sent and a one fault is received in the following word, the fault is a short-to-ground / overtemperature for high-side drive or short-to-battery/overtemperature for low-side drive. The timing between two write words must be greater than 300 s to allow adequate time to sense and report the proper fault status.
OVERVOLTAGE FAULT
An overvoltage condition on the VPWR pin will cause the device to shut down all outputs until the overvoltage condition is removed. When the overvoltage condition is removed, the outputs will resume their previous state. This device does not detect an overvoltage on the VDD pin. The overvoltage threshold on the VPWR pin is specified as VPWR(OV) V, with 1.0 V typical hysteresis. A VPWR overvoltage detection is global, causing all outputs to be turned OFF.
OUTPUT OFF OPEN LOAD FAULT
An output OFF open load fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). The Output OFF Open Load fault is detected by comparing the drain-to-source voltage of the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose.
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FUNCTIONAL DESCRIPTION DEVICE OPERATION
An output OFF open load fault is indicated when the drainto-source voltage is less than the output threshold voltage (VOUT(flt-th)) of 2.5 V to 4.0 V. Hence, the 33879 will declare the load open in the OFF state when the output drain-tosource voltage is less than VOUT(flt-th). This device has an internal 80 A current source connected from drain to source of the output MOSFET. The current source may be programmed on or off via SPI. The Power-ON Reset state for the current source is "off" and must be enabled via SPI. To achieve low Sleep mode quiescent currents, the Open Load Detection Current source of each driver is switched off when VDD or EN is removed. During output switching, especially with capacitive loads, a false output OFF open load fault may be triggered. To prevent this false fault from being reported, an internal fault filter of 100 s to 300 s is incorporated. A false fault reporting is a function of the load impedance, RDS(ON), COUT of the MOSFET, as well as the supply voltage, VPWR. The rising edge of CS triggers the built-in fault delay timer. The timer will time out before the fault comparator is enabled and the fault is detected. Once the condition causing the open load fault is removed, the device will resume normal operation. The open load fault, however, will be latched in the output DO register for the MCU to read.
OUTPUT VOLTAGE CLAMP
Each output of the 33879 incorporates an internal voltage clamp to provide fast turn-off and transient protection of each output. Each clamp independently limits the drain-to-source voltage to 45 V for low-side drive configurations and -20 V for high-side drive configurations. The total energy clamped (E J) can be calculated by multiplying the current area under the current curve (I A) times the clamp voltage (V CL) (see Figure 18). Characterization of the output clamps, using a single pulse non-repetitive method at 0.35 A, indicates the maximum energy per output to be 50 mJ at 150C junction temperature.
Drain-to-Source Clamp Voltage (V CL = 45 V)
Drain Voltage
Drain Current (I D = 0.3 A)
Clamp Energy (E J = I A x V CL)
Drain-to-Source ON Voltage (V DS(ON))
GND
Current Area (I A)
Time BAT
SHORTED LOAD FAULT
A shorted load (overcurrent) fault can be caused by any output being shorted directly to supply, or an output experiencing a current greater than the current limit. There are two safety circuits progressively in operation during load short conditions that provide system protection: 1. The device's output current is monitored in an analog fashion using SENSEFET approach and current limited. 2. The device's output thermal limit is sensed and when attained causes only the specific faulted output to shut www..com down. The output will remain off until cooled. The device will then reassert the output automatically. The cycle will continue until fault is removed or the command bit instructs the output off. Shorted load faults will be reported properly through SPI regardless of Open Load Detection Current enable bits.
Drain-to-Source ON Voltage (V DS(ON)) VS
GND
Current Area (I A)
Time
Clamp Energy (E J = I A x V CL)
Source Current
(I S = 0.3 A) Source Clamp Voltage (V CL = -15 V)
Source Voltage
Figure 18. Output Voltage Clamping
SPI CONFIGURATIONS
The SPI configuration on the 33879 device is consistent with other devices in the Octal Serial Switch (OSS) family. This device may be used in serial SPI or parallel SPI with the 33298 and 33291. Different SPI configurations may be provided. For more information, contact Freescale Analog Products Division or local Freescale representative.
UNDERVOLTAGE SHUTDOWN
An undervoltage condition on VDD or VPWR will result in the shutdown of all outputs. The VDD undervoltage threshold is between 0.8 V and 3.0 V. VPWR undervoltage threshold is between 3.0 V and 5.0 V. When the supplies fall below their respective thresholds, all outputs are turned OFF. As both supplies returns to normal levels, internal logic is reset and the device resumes normal operation.
REVERSE BATTERY
The 33879 has been designed with reverse battery protection on the VPWR pin. All outputs consist of a power MOSFET with an integral substrate diode. During the reverse battery condition, current will flow through the load via the substrate diode. Under this circumstance, relays may energize and lamps will turn on. Where load reverse battery protection is desired, a reverse battery blocking diode must be placed in series with the load.
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search using the "98A" drawing number listed below.
DWB SUFFIX EK (Pb-FREE) SUFFIX 32-LEAD SOICW EXPOSED PAD PLASTIC PACKAGE 98ARL10543D ISSUE O
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PACKAGING PACKAGE DIMENSIONS
PACKAGE DIMENSIONS (CONTINUED)
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 5.0
DATE 2/2006
DESCRIPTION OF CHANGES * * * * * * * * * * Page 2, Figure 1; An exposed pad internal block and EP pin have been added to the internal block diagram. Page 4, Table 1; Table 1 has been updated to reflect the Exposed pad pin and pin definition. Page 6, Table 3; Logic Supply Sleep State Hysteresis and Note 7 have been removed. The VDD Supply contains no hysteresis. Page 7, Table 3; Output Fault Detection Current @ Threshold, High-Side Configuration Max parameter has been increased from 70uA to 90uA. Page 7, Table 3; Output OFF Open Load Detection Current, High-Side Configuration has been updated to reflect the voltage of the VPWR pin during the parameter test. Page 7, Table 3; Output OFF Open Load Detection Current, Low-Side Configuration has been updated to reflect the voltage of the VPWR pin during the parameter test. Page 7, Table 3; Output Leakage Current High-Side and Low-Side Configuration Max parameter has been decreased from 7uA to 5uA. Page 15, Functional Pin Description; A description has been added for the Exposed Pad pin. Page 1, Device isometric; Corrected orientation of IC pin 1 from top left to bottom right. ALL Pages; Updated Data Sheet to reflect Freescale formatting. Added 33879A version Added MCZ33879EK/R2 and MCZ33879AEK/R2 to the Ordering Information Added Device Variations on page 2 Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Rations on page 6. Added note with instructions from www.freescale.com. Changed Output Fault Detection Voltage Threshold (7) on page 8 Renumbered X axis on Figure 14 - Open Load Detection Threshold vs. Temperature on page 14 Changed Overvoltage on page 18 and Overvoltage Fault on page 19
6.0
6/2007
* * * * * * *
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MC33879 Rev 6.0 6/2007

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